Arquiteturas de hardware para redes neurais convolucionais visando compromisso entre custo e desempenho

Abstract

Convolutional neural networks, especially when embedded in devices with low power consumption requirements, present a significant challenge: balancing the typically high precision expected of neural networks, response time, and the demands on computational, logical, and memory resources. This work presents three hardware architectures for convolutional neural networks with high degree of parallelism and component reuse implemented in a programmable device. The first design, which is termed memoryful architecture, uses as much memory as necessary to store the input data and intermediate results. The second design, which is termed memoryless architecture, defines and explores a specific input sequencing pattern to completely avoid the use of RAM. The third design, which is termed cache memory-based architecture, is an intermediate solution, where the standardization of the input sequence is also explored but an auxiliary memory is used to store some intermediate results and, consequently, improve processing time. We compare the three designs in terms of power, area and processing time. Allowing memory usage increases overall hardware cost but reduces processing time. At the other end, completely eliminating memory usage increases operation parallelism, but compromises processing time. A trade-off between memory usage and processing performance is achieved in the cache memory-based architecture that optimizes processing time but at a cost in terms of hardware resources.